Silicon Calculator

Silicon Calculator Summary

The thought of designing my own silicon wafer seemed like a very far out dream until this project. Any time I have used an integrated circuit (IC), I always find it absolutely mind blowing how it was designed. A class at Iowa State University allowed me to design my own silicon IC and have it fabricated for free! For this me and one partner were tasked with creating a calculator that could add, subtract, multiply, and divide while producing an output that could be read on a 7 segment display. This project took a lot of work and was very design and code heavy. In addition previous labs in this class helped us learn the math required for creating minimally sized mosfets, diodes, resistors and capacitors that will be needed throughout this project.

Techical Specifications

# of Gates : Approximately 1500

# of Transistors : Approximately 3700

Language : Verilog

Simulation Program : Modelsim

Layout Program : Virtuoso

The Design

To start working on this project, the first major step was working on the design for all of the digital logic needed for this circuit. Several major components are needed and some will be used multiple times. I first used Gitlab to create a graph showing what components we needed to create shown below.

After having a starting point for what needed to be created, I started working through the digital logic needed for each component. I took advantage of one of my favorite campus resources, Massive Whiteboards, and drew out most of the major components as pictured below. Most of the designs were quite basic in terms of digital logic and I was able to draw them all from memory up until the Non-Restoring Divider. This module took the longest amount of time. I tried very hard to design a divider using shift right techniques however it became increasingly difficult to create an algorithm that worked for variables yet had a finite minimized number of gates. In the end I found a resource online that proposed a design very similar to the one I have draw. It uses a relatively small number of gates for an Nbit divider.

After all the major components were roughly drawn out, It was time to implement them in Verilog. Up until this point, I have not used very much Verilog and have focused on VHDL instead so there was a bit of a learning curve. Even with the learning curve however, we were using structural modeling and VHDL is very similar in how structuring works. This made the switch to Verilog easy enough to learn in a couple weeks. After we completed the smaller Verilog modules, we started designing the full systems level diagram. This diagram described how the calculator would actually work.

System Description

Here is the System Description exert from the Project Paper written for this class:

"This calculator was fairly simple in design. It was laid out in a similar manner to a multi cycle processor ALU. To produce a result, the values are stored in the input registers labeled A register and B register on the following diagram. The registers are a series of D flip flops that are configured such that their output is always enabled, and they require a positive edge clock to load. The registers are tied to the load pin and reset pin for control. The registers continuously output their stored value which causes the ALU to always output a calculated value. In our case we parallelized the ALU into 3 units, Divide, Multiply, and AddSub for addition and subtraction. The value of both the A and B registers is passed to all three ALU units. After the ALU provides an output, the function selection chooses which output to apply to the result register. This mux is a 4 to 1 12 bit wide mux. However, since the AddSub’s output is the same, only three of the 4 mux inputs are used. After the mux selects the proper output, it stores it similar to how a real calculator's equal button works. The results register stores the output of the ALU and outputs its data to both the return mux, and the decode/hex display. Without this register, there is a positive feedback during the writeback operation due to the lack of edge detection on the DFFs used in the A register. This register prevents the feedback loop unless the load bit and write back bit are not both logic High. The logic table below shows which operations are performed with various logic levels."

System Level Diagram

Truth Table

After we had all the Verilog written, created test benches to test and verify all our modules. These were generally very simple test benches that consisted of typical case tests rather than edge case. After ensuring our Verilog works as expected, we moved on to the synthesis. To do the synthesis we used a program called Genus that is packaged into the Virtuoso toolkit. More on Virtuoso later. Genus allowed us to provide our Verilog, and it would synthesize using a predetermined set of logic gates. We were provided a list of minimally sized gates that used the ON Semiconductor 0.5nm process. Each of these gates were described in a schematic and provided to Genus to develop our circuit. Below is the high level drawing of our circuit schematic.

Synthesis

This view shows the block diagram that was initially compiled by Genus. After this view, it compiled the gate level view. The next step after generating the gate level view was creating an optimized schematic. To do this we used another tool called Innovus. This used the list of gates provided and simplified our raw design with these gate. Finally we used the synthesized version to generate a layout. The layout looks very unoptimized as there is no blocking seen in most modern processors. However It does have a proper layout and design rule check.

expanded Gate Level Drawing

Optimized gate level drawing

Automatic Layout of Mosfets

Zoomed in view where you can see the wires

Conclusion

In conclusion, this project was really cool. Hopefully In the future I can send these design files to a silicon fabrication house to have my die created on a wafer as I think that would be super cool. This project was quite fun as it gave almost complete freedom for the design in Verilog. Additionally I learned how both binary multiplication and division worked in hardware and different strategies for optimization. I enjoyed this project and hope I can continue with projects similar to this in the future.